VLSI Design Engineer

  • No of position : 10
  • Experience: 1 years
  • Deadline: 1st May, 2019
  • No of position : 10
  • Role : VLSI Design Engineer
  • Skill : VLSI design
  • Employment Status : Full Time

Job Responsibilities

  • IC design using HDL (Verilog preferred)
  • Have good knowledge on VLSI design methodology
  • Hands on experience on ASIC/LSI design

Additional Requirements

  • Age at least 22 years
  • Both males and females are allowed to apply.
  • Good communication skill
  • Quick Learner
  • Interested to go to Japan
  • Education : Graduate in EEE or Applied Physics