VLSI Design Engineer

  • No of position : 04
  • Experience: # At least 1 year(s) # The applicants should have experience in the following area(s): ASIC, FPGA, HDL, logic, LSI, RTL, VLSI
  • Deadline: 12th February, 2020
  • No of position : 04
  • Role : VLSI Design Engineer
  • Skill : VLSI design methodology
  • Employment Status : Full Time

Job Responsibilities

  • IC Design using HDL (Verilog preferred)

 

Additional Requirements

  • Age at least 22 years
  • Both males and females are allowed to apply.
  • Have good knowledge on VLSI design methodology
  • Hands on experience on ASIC/LSI design
  • Logic Design
  • -Specification Study
  • -Specification Design
  • -RTL Coding Experience
  • -Can use Verilog HDL
  • Logic Design Verification
  • -Make Validation Specification
  • -Waveform Verification
  • -RTL Verification
  • -Use SystemVerilog
  • Building Logic Design Verification Environment
  • -UVM (Universal Verification Methodology) Environment Building
  • SVA (SystemVerilog Assertion)/Formal Verification
  • -Generate SVA Script
  • -Formal Verification
  • -Building Behavior Model for Verification Regardless of Language Used
  • -Can use Object-oriented Language like C++, SystemC
  • Logic Synthesis
  • -Generate Logic Synthesis Script
  • -STA (Static Timing Analysis)
  • -DFT (Design for Testability) Synthesis
  • -Scan path insertion
  • FPGA Programming
  • Analog IC Circuit Design and Verification Experience
  • -Basic Analog Circuit Design such as Op-amp.
  • -Reference Voltage Source. Reference Current Source
  • -Understand Analog IC Product Specification
  • -Various Analog Circuit Verification
  • -Generate Technical Documents such as Simulation Summary. IC Evaluation Report
  • -Handle Cadence Tool such as Virtuoso IC6. Spectre
  • AMS (Analog Mixed Signal) IC Design
  • -Brief Analog Simulation Model Generation Using Verilog-A
  • -ISO26262(Functional Safety) Compliant Design
  • Good communication skill
  • Quick Learner
  • Interested to go to Japan

 

Compensation & other benefits

  • Weekly 2 holidays, Over time allowance
  • Salary Review: Yearly
  • Festival Bonus: 2 (Yearly)

 

  • Education : Graduate in EEE or Applied Physics or any other relevant subjects